1. Field of the Invention
This disclosure relates, in general, to semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device having 3-level memory cells, and methods of operating the non-volatile semiconductor memory device.
2. Description of the Related Art
Non-volatile semiconductor memory devices preserve stored data when power is disconnected therefrom. Various types of memory cells appropriate for non-volatile semiconductor memory devices have been known. One such memory cell for a non-volatile semiconductor memory device is a single transistor type memory cell.
In general, a transistor type memory cell MC, as shown in FIG. 1, includes a source S and a drain D on a semiconductor substrate, a floating gate FG formed between a dielectric oxide film DOX and a gate oxide film GOX, and a control gate CG. The floating gate FG traps electrons. The trapped electrons establish the threshold voltage of the memory cell MC. When the non-volatile semiconductor memory device operates in a read operation, the threshold voltage of the memory cell MC is detected, and detected data is stored therein.
Typically, in the memory cells MCs of the non-volatile semiconductor memory device, program and erase operations may be repeatedly performed. The various functions of single transistor memory cells MCs are determined by various types of applied voltage. Such a single transistor memory cell MC is programmed as electrons move to the floating gate FG. Electrons may move to the floating gate FG by Fowler-Nordheim tunneling (FN) or electron injection. The electron injection may be Channel Hot-Electron injection (CHE) or Channel-Initiated Secondary Electron Injection (CISEI). FN is widely used in flash memory that erases data all at one time.
In general, the transistor memory cell MC stores one of two values. The two data values, as illustrated in FIG. 2, are stored by a threshold value that is set to one of two levels. For example, data are read as “1” when the threshold voltage of the memory cell MC is lower than a reference voltage VM, whereas data are read as “0” when the threshold voltage of the memory cell MC is higher than the reference voltage VM.
As semiconductor memory devices have become highly integrated, a 4-level memory cell has been developed. The 4-level memory cell, as illustrated in FIG. 3, may be programmed to one of four threshold voltage levels. As a result, the 4-level memory cell can store one of four types of data. Therefore, a non-volatile semiconductor memory device having 4-level memory cells (hereinafter referred to as a ‘4-level non-volatile semiconductor memory device’) has data storage capacity two times that of a non-volatile semiconductor memory device having 2-level memory cells (hereinafter referred to as a ‘2-level non-volatile semiconductor memory device’).
In 4-level memory cells, the margin between the threshold voltage of neighboring levels is typically 0.67 V, which is very narrow. The threshold voltage of each memory cell may shift due to the leakage of electrons, etc. Accordingly, the threshold voltage of the memory cell MC programmed to one of the 4 threshold levels may shift to a neighboring threshold voltage. As a result, the 4-level non-volatile semiconductor memory device has the problem of low reliability.
Furthermore, in the 4-level memory cell, the margin between the threshold voltages of neighboring levels is very narrow, and a program voltage applied to the control gate of the memory cell requires increments having very narrow intervals. Accordingly, the 4-level non-volatile semiconductor memory device has a problem in that the time required for programming is very long.
In order to improve the reliability of the 4-level memory cell and reduce the time required for programming, a non-volatile semiconductor memory device having 3-level memory cells (hereinafter referred to as a ‘3-level non-volatile semiconductor memory device’) have been proposed.
The 3-level memory cell MC, as illustrated in FIG. 4, has 3-level threshold voltage groups G1, G2 and G3. In this case, two memory cells MC form a set and operate to store 3-bit data.
Therefore, the 3-level memory cell has a larger number of storage states compared to the 2-level memory cell, thus having a relatively higher degree of integration. Furthermore, the 3-level memory cell has larger intervals between threshold voltage groups than does the 4-level memory cell. Thus, the 3-level memory cell has relatively higher reliability and the time required for programming is relatively reduced.
Meanwhile, the existing 3-level non-volatile semiconductor memory device, as illustrated in FIG. 5, uses a method of reading a 3-level (G1, G2, G3) state from each of the two memory cells MC1 and MC2 and converting read states into 3-bit (BIT1, BIT2 and BIT3) information as a basic operation. Therefore, the existing 3-level non-volatile semiconductor memory device, as illustrated in FIG. 6, has a disadvantage in that it requires a 3-level code conversion circuit 40 between a page buffer 20 and a data Input/Output (I/O) line 30, so that restrictions to layout increase.
Furthermore, in the existing 3-level non-volatile semiconductor memory device, a 3-bit data value is determined by examining a 3-level state of each of the two memory cells at the time of a read operation. Accordingly, even in the case where a one-bit data value is determined, a total of four data fetch operations are required. As a result, the existing 3-level non-volatile semiconductor memory device has the disadvantage of overall low fetch speed.
Moreover, in the existing 3-level non-volatile semiconductor memory device, two memory cells are sequentially programmed at the time of programming, so that it has the disadvantage of overall low programming speed.